The subject matter relates to a semiconductor design technology, and more particularly, to a semiconductor memory device that generates a strobe signal for sensing and amplifying input and output by responding to a main strobe signal, and an operation method thereof.
In general, a semiconductor memory device including a double data rate synchronous DRAM (DDR SDRAM) generates a main strobe signal in response to a column address strobe (CAS) signal as a column command. The main strobe signal becomes a source signal to generate a column based main signal as a pulse signal having an activation width corresponding to an external clock signal. In the semiconductor memory device, a column selection signal, a write drive enable signal, a local input/output line pre-charging signal and an input/output sense amplifying strobe signal and the like are generated by using the main strobe signal. Here, the column selection signal, the write drive enable signal, the local input/output line pre-charging signal and the input/output sense amplifying strobe signal have the same activation width.
FIG. 1 is a circuit diagram showing input/output operations of a conventional semiconductor memory device.
Referring to FIG. 1, inspecting briefly a reading operation. If a word line WL selected by decoding a row address supplied from an outside during the reading operation is activated, a cell transistor T1 of a semiconductor memory cell 110 turns on and a charge for data stored in a cell capacitor C1 is charge shared to pre-charged main/sub bit lines BL and /BL. The main bit line BL and the sub bit line /BL have a fine voltage difference through a charge sharing operation. For reference, a pre-charged voltage level is at half the voltage level of a core voltage as an inner voltage.
Thereafter, a bit line sense amplifier 120 senses fine voltages of the main bit line BL and the sub bit line /BL corresponding to the main bit line BL to amplify the sensed fine voltages. In other words, if a potential of the main bit line BL is higher than a potential of the sub bit line /BL, the main bit line BL is amplified to a pull-up power voltage RTO and the sub bit line is amplified to a pull-down power voltage SB. Whereas, if a potential of the main bit line is lower than that of the sub bit line, the main bit line BL is amplified to the pull-down power voltage SB and the sub bit line /SB is amplified to the pull-up power voltage RTO.
On the other hand, if a column selection unit 130 is activated in response to a column selection signal YI selected by decoding a column address applied from an outside, the main and sub bit lines BL and /BL are connected to main and sub segment input/output lines SIO and /SIO. That is, the data amplified at the main bit line BL is transferred to the main segment input/output line SIO and the data amplified at the sub bit line /BL is transferred to the sub segment input/output line /SIO. Thereafter, if an input/output switching unit 140 is activated in response to an input/output control signal CTR_IO, the main and sub segment input/output segment lines are connected to main and sub local input/output lines LIO and /LIO. That is, the data transferred to the main segment input/output line SIO is transferred to the main local input/output line LIO and the data transferred to the sub segment input/output line /SIO is transferred to the sub local input/output line /LIO. A read driving unit 150 drives a global input/output line GIO according to the data transferred through the main and sub local input/output lines LIO and /LIO.
Finally, the data stored at the memory cell 110 is transferred to the main and sub segment input/output lines SIO and /SIO at the main and sub bit lines BL and /BL, to the main and sub local input/output lines LIO and /LIO at the main and sub segment input/output lines SIO and /SIO and to the global input/output line GIO at the main and sub local input/output lines LIO and /LIO.
Meanwhile, the data applied from an outside during a writing operation is transferred in an opposite direction of the reading operation. That is, the data applied from the external is transferred to the main and sub local input/output lines LIO and /LIO through a write driving unit 160 at the global input/output line GIO, to the main and sub segment input/output lines SIO and /SIO at the main and sub local input/output lines LIO and /LIO and to the main and sub bit lines BL and /BL at the main and sub segment input/output lines SIO and /SIO. The transferred data is finally stored in the cell memory.
For reference, the data transferred through each line reflect an RC loading by a plurality of resistors R and capacitors C shown in FIG. 1.
FIG. 2 is a diagram showing the read driving unit 150 of FIG. 1.
Referring to FIG. 2, the read driving unit 150 includes an input/output sense amplifying unit 210 and a main driving unit 230.
The input/output sense amplifying unit 210 sense amplifies the signals applied to the main and sub local input/output lines LIO and /LIO in response to an input/output sense amplifying strobe signal STB_IOSA and generates pull-up and pull down control signals CTR_PU and CTR_PD corresponding thereto. That is, the pull-up control signal CTR_PU is activated in response to the data applied to the main local input/output line LIO and the pull-down control signal CTR_PD is activated in response to the data applied to the sub local input/output line /LIO. Herein, the input/output sense amplifying strobe signal STB_IOSA is generated by using the main strobe signal (not shown) described above and the input/output sense amplifying unit 210 performs the sense amplifying operation in response to the input/output sense amplifying strobe signal STB_IOSA.
A main driving unit 230 drives the global input/output line GIO in response to the pull-up and pull-down control signals CTR-PU and CTR_PD. That is, the main driving unit 230 performs a pull-up operation to the global input/output line in response to the pull-up control signal CTR_PU and performs a pull-down operation to the global input/output line GIO in response to the pull-down control signal CTR_PD.
Herein, the input/output sense amplifying strobe signal STB_IOSA will be examined. As described above, the input/output sense amplifying strobe signal STB_IOSA is a signal generated in response to the main strobe signal. That is, if the main strobe signal has an activation width of 1 tCK, the input/output sense amplifying strobe signal STB_IOSA also has an activation width of 1 tCK. Therefore, the input/output sense amplifying unit 210 operating in response to the input/output sense amplifying strobe signal STB_IOSA also performs the sense amplifying operation during the activation time of 1 tCK.
On the other hand, an external clock signal has been gradually designed to operate at high frequency for increasing an operation speed of the semiconductor memory device. That is, the time corresponding to the 1 tCK has been gradually shortened. As the time corresponding to the 1 tCK of the external clock signal becomes short, accordingly an activation width of the main strobe signal becomes narrow, an activation width of the input/output sense amplifying strobe signal STB_IOSA becomes narrow, and a time for performing a sense amplifying operation of the input/output sense amplifying unit 210 decreases. Thus, the time to sense amplify the data applied to the main and sub local input/output lines LIO and /LIO as well as the time to drive the global input/output line GIO becomes short. As a result, if the semiconductor memory device operates at a high frequency, but the data does not perform a full swing to the global input/output line GIO, this can cause errors in the semiconductor memory device.